
# PlanAhead Launch Script for Pre-Synthesis Floorplanning, created by Project Navigator

create_project -name an108_adda_vga_test -dir "C:/Users/admin/Desktop/test/planAhead_run_3" -part xc6slx9ftg256-2
set_param project.pinAheadLayout yes
set srcset [get_property srcset [current_run -impl]]
set_property target_constrs_file "an108_adda_vga_test.ucf" [current_fileset -constrset]
set hdlfile [add_files [list {ipcore_dir/adda_pll.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {ipcore_dir/video_pll.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
add_files [list {ipcore_dir/da_rom.ngc}]
add_files [list {ipcore_dir/dpram1024x8.ngc}]
set hdlfile [add_files [list {src/timing_gen_xy.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {ipcore_dir/dpram1024x8.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {src/wav_display.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {src/key_filter.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {src/grid_display.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {src/color_bar.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {src/ad9280_sample.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {ipcore_dir/da_rom.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {src/top.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set_property top top $srcset
add_files [list {an108_adda_vga_test.ucf}] -fileset [get_property constrset [current_run]]
add_files [list {ipcore_dir/da_rom.ncf}] -fileset [get_property constrset [current_run]]
add_files [list {ipcore_dir/dpram1024x8.ncf}] -fileset [get_property constrset [current_run]]
open_rtl_design -part xc6slx9ftg256-2
